The present invention relates to interconnection structures, including interlevel interconnection structures, devices containing these structures, and methods of making these structures and devices.
Typically, interconnection structures between conductive layers in an integrated circuit are known as contacts or vias (hereinafter “vias”), which are typically metallic structures that have ends in electrical contact with the conductive, layers. The vias are typically formed by depositing a dielectric layer over a first conductive layer, etching a hole through the dielectric layer, filling the holes with a conductor material to form the vias (and optionally, the overlying conductive layer), then etching or polishing away any excess conductor material. If the via material differs from that of the overlying conductive layer, then one typically forms a second conductive layer on top of the vias and the dielectric material after removing the excess via conductor material.
One approach to connecting an upper conductive layer with a lower conductive layer is called “dual damascene” or “in-laid” metallization. This approach is illustrated in FIGS. 1-3. In FIG. 3, a view from above, a lower conductive layer 2 is electrically connected to an upper conductive layer 10 by a via 14 which has one end in contact with the lower conductive layer, and the other end in contact with the upper conductive layer. The conductive layer is in-laid into an upper dielectric layer 8. The via typically has a circular cross section. In the illustration the portion of the conductive layer shown is in the pattern of a wire, but any overall pattern is possible. The x- and y-axes included in the figure indicate the orientation of the side views shown in FIGS. 1 and 2.
FIG. 1 illustrates a side view along the x-axis of FIG. 3. Shown are upper conductive layer 10, the lower conductive layer 2, the via 14, and the upper dielectric layer 8. A larger portion of the upper conductive layer is shown than in FIG. 3, and therefore more than just a wire portion of the pattern of this layer is visible. Also shown are an etch-stop layer 6, and a lower dielectric layer 4. A view perpendicular to that of FIG. 1 is shown in FIG. 2. The figures show the via electrically connecting a lower conductive layer with an upper conductive layer.
A first technique, which allows for self-alignment, is illustrated in FIGS. 4-7. Starting with FIG. 4, a photoresist layer 16 is patterned on a structure including a lower conductive layer 2, a lower dielectric layer 4 on the lower conductive layer, an etch-stop layer 6 on the lower dielectric layer, and an upper dielectric layer 8 on the etch-stop layer. The pattern of the photoresist layer is that of the cross section of the via that will be formed. Next, as shown in FIG. 5, the upper dielectric layer 8 is etched.
The photoresist layer is then removed, and a new photoresist layer 16 is formed on the structure, which is patterned, as illustrated in FIG. 6. This pattern corresponds to the cross section of the upper conductive layer. The upper and lower dielectric layers are then etched, to form the via hole 18 as well as the upper conductive layer trench 12, as illustrated in FIG. 7. Finally, the photoresist layer is removed and a conductive material is filled into the via hole and the upper conductive layer trench, to form the structures shown in FIGS. 1-3.
In this first technique, the second etching that forms the via hole and the upper conductive layer trench is difficult, since the greater the aspect ratio (i.e., height to width) of the hole, the less reliably the hole is formed. When the height of the photoresist layer is included, the aspect ratio of the via hole may be 8:1 or more. In addition, if the second photolithography step is sufficiently misaligned, photoresist may remain in the via hole in the upper insulating layer (see FIG. 6(b)), and result in a via sidewall slope that does not permit effective electrical contact between the resulting via and the underlying conductive layer (see FIG. 7(b)).
A second technique used to form these structures is illustrated in FIGS. 8-11. Starting with FIG. 8, a photoresist layer 16 is patterned on a structure including a lower conductive layer 2, a lower dielectric layer 4 on the lower conductive layer, and an etch-stop layer 6 on the lower dielectric layer. The pattern of the photoresist layer is that of the cross section of the via that will be formed. Next, as shown in FIG. 9, the etch-stop layer 6 is selectively etched to avoid etching the underlying dielectric layer.
The photoresist layer is then removed, and an upper dielectric layer 8 is formed on the structure, followed by a photoresist layer 16, which is patterned, as illustrated in FIG. 10. This pattern corresponds to the cross section of the upper conductive layer. The upper (and, where subsequently exposed, lower) dielectric layer(s) are then etched, to form the via hole 18 as well as the upper conductive layer trench 12, as illustrated in FIG. 11. Finally, the photoresist layer is removed and a conductive material is filled into the via hole and the upper conductive layer trench, to form the structures shown in FIGS. 1-3.
In this second technique, an effective via opening will depend on the accuracy of alignment between the via mask and the trench mask used to pattern the photoresist layers (earlier and later photoresist layers, respectively). Proper alignment becomes more and more difficult as the size of the structures becomes smaller and smaller, and effective via openings may be quite difficult to produce at a width of 0.18 μm and smaller.